Ramaiah Skill Academy (RSA)
ASIC RTL Design and Verification Training Program
Certification (IT & Software)
Shortlisted by 0+ Students
Location: Bengaluru/Bangalore
Duration: 6 MONTH
Regular / Offline
Average Fees: ₹ 82600
Highlights The ASIC RTL Design and Verification Training Program gives you a strong base in digital design and hands-on verification. You’ll work with key tools like Verilog, System Verilog, UVM, and scripting languages such as Python, TCL, and Linux. The course teaches you how to write synthesizable RTL code, build UVM-based test benches, and verify designs using real-world techniques like constrained random testing, assertions, and coverage analysis. You’ll also learn how to debug issues, apply formal verification, and work with AMBA protocols to test IPs and SoC components. By the end, you’ll be ready to take on design and verification roles in the VLSI industry with confidence.
Indicative Content for ASIC RTL Design and Verification Program
| Foundation | Verilog & System Verilog | UVM | Career Guidance |
Linux Essentials TCL Scripting Python Scripting Digital Design High Speed Digital Design Static Timing Analysis Verilog HDL Basics Introduction to EDA tools
| Verilog for Synthesis Verilog based design & Verification System Verilog: Introduction Testbench Architecture interfaces, classes OOPS concepts Assertions Arrays SV Advanced Procedural Statements and Routines Threads and IPC Direct Programming Interface (DPI) Randomization and constraints Code Coverage & Functional Coverage Formal Verification Assertion Based Verification Coverage driven Verification AMBA Protocols | Introduction to UVM UVM Testbench Architecture UVM Base Classes UVM Phases & Reporting Mechanisms Transaction Level Modelling Factory Registration & Methods Virtual Sequence & Sequencer Register Abstraction Layer Config DB Project | Soft Skills Building Resume Mock Interviews Personality Development Report Writing |
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