Attention: Students and Graduates of Engineering and Science

Physical Design and Verification Trainee

Location: Bangalore

Duration: 6 Months

Physical Design and Verification Trainee - Key Learnings for Trainee

• Build a foundation in CMOS and advanced device technologies like FinFET, GAA, and SOI, along with scripting in Python and TCL.
• Gain hands-on experience in IC design flows using professional EDA tools, covering logic synthesis, placement and routing, clock tree synthesis, and timing closure.
• Learn and apply Design for Test (DFT) techniques such as scan chains, ATPG, and BIST for real-world chip tape-out processes.
• Perform signoff checks including DRC, LVS, ERC, and antenna rule verification, ensuring design readiness for fabrication.
• Analyze and resolve challenges like IR drop, crosstalk, routing congestion, and study post-layout performance under PVT variations.

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