Executive Cert in VLSI Physical Design & Signoff
Certification (IT & Software)
Shortlisted by 50+ Students
Location: Bengaluru/Bangalore
Duration: 9 MONTH
Online / Virtual
Average Fees: ₹ 2 Lakhs
Highlights In the AI age, chip makers are ready to make the most of their potential by using EDA tools that are AI-supported, IP libraries that have been validated in silicon, and open computing solutions like RISC-V to design and make efficient SoCs that are powerful. With these developments, the most difficult SoCs can be made for the products of the future. But timing closure, power optimization, and area efficiency in physical design are very important for the first-pass silicon to be successful. It is now the right moment for silicon designers and VLSI lovers to go through ASIC Physical Design methodologies, which include the entire flow from RTL to GDSII, and besides that, the techniques for the different stages of synthesis, floor planning, placement, clock tree synthesis, routing, timing analysis, power optimization, and sign-off for successful tape-outs.
Executive Certification in VLSI Physical Design and Signoff - iHUB, IIT Roorkee
The VLSI Physical design and verification course is a thorough one. First, the learners familiarize themselves with VLSI, Moore's Law, SoC architecture, and design flows which are the main reasons that make the course advances. The next step is the digital logic fundamentals that teach the following: number systems, combinational and sequential circuits, FSMs, and memory design. The course then introduces practical hardware design and verification using Verilog HDL programming - coding styles, FSM designs, and lab exercises. Next, the students learn about device physics and CMOS fundamentals like MOSFET operation, CMOS fabrication, and circuit layout.
In the DFT module, the focus is on testing, ATPG, scan insertion, and fault modeling which are all parts of verification, coupled with developing automation skills through TCL and Python scripting. Students also go through version control techniques using Git and then move on to ASIC physical design flow, which comprises of floor planning, placement, CTS, routing, STA, layout compaction, and physical verification (DRC, LVS, IR drop, EM). Students also get to learn about advanced topics of signal integrity, low-power verification with UPF, and power-aware checks. Thus, the course ensures that the students have the expertise from RTL coding to Chip tape-out as they go through the trained labs and industry-aligned projects.
Program Highlights
Executive Certification in VLSI Physical Design and Signoff with Placements Fees Details:
Total Fees for 9 Months Programme: INR 2,00,000 + GSP
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