Physical Design and Verification Training Program

The Physical Design and Verification Training Program is built for students who want to understand how a chip is physically constructed and made ready for manufacturing. You'll start by learning the basics of CMOS and advanced device technologies like FinFET, GAA, and SOI, while building scripting skills in Python and TCL to automate tasks. From there, the program dives into full custom and semi-custom IC design using professional EDA tools, covering everything from digital logic synthesis and PnR to clock tree synthesis and timing closure.

You'll also get hands-on experience in applying Design for Test (DFT) concepts—like scan chains, ATPG, and BIST—just like it's done in real chip tape out processes. As you progress, you'll build full design flows from netlist to GDSII, including essential signoff checks like DRC, LVS, ERC, and antenna rule verification. You'll tackle challenges such as IR drop, crosstalk, and routing congestion, and analyze post-layout performance under PVT variations. By the end, you'll be capable of handling complex physical design tasks, preparing you for critical roles in VLSI and ASIC implementation teams.

Program Outcomes:

• Discuss the core concepts of physical design principles, device physics, CMOS and advanced CMOS technologies including FinFET, GAA (Gate-All-Around), SOI (Silicon-On-Insulator)  and Scripting Languages like Python and TCL 
• To apply core concepts of digital logic, synthesis, timing and power analysis to design, implement, and validate full-custom and semi-custom digital ICs using industry-standard EDA tools. 
• To implement Design for Test (DFT) concepts, including scan chain insertion, ATPG (Automatic Test Pattern Generation), and BIST (Built-In Self-Test) in scenarios mimicking realistic tapeout processes. 
• Develop complete physical design flows, including floorplanning, Placement and Routing (PnR), Clock Tree Synthesis (CTS), power, Performance and area(PPA) .Engineering Change Orders (ECOs), and signoff methodologies. 
• Implement the complete ASIC physical design flow from netlist to GDSII using industry tools (e.g., Cadence Innovus, Synopsys ICC2), including physical verification steps like DRC, LVS, ERC, and Antenna Checks, and resolving associated violations. 
• Perform Static Timing Analysis (STA) and power-aware validation while addressing critical design metrics such as IR drop, crosstalk, routing congestion, signal integrity, and parasitics. 
• Analyze post-layout simulation results under PVT variations, iterate to meet performance targets, and apply mitigation techniques for challenges in advanced technology nodes. 

Duration: 6 Months

Fees Structure: INR 70,000 + GST

Total Fees: INR 82,600

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