Ramaiah Skill Academy (RSA)
Physical Design and Verification Training Program
Certification (IT & Software)
Shortlisted by 0+ Students
Location: Bengaluru/Bangalore
Duration: 6 MONTH
Regular / Offline
Average Fees: ₹ 82600
Highlights This training program introduces you to the complete flow of physical chip design, from logic to layout. You'll learn about CMOS, FinFET, GAA, and SOI technologies, and get hands-on experience with tools like Python, TCL, and industry EDA software. The course teaches key concepts such as floor planning, placement and routing, clock tree synthesis, and timing analysis. You'll also practice DFT methods like scan insertion and BIST, and learn how to verify and prepare your design for real-world chip fabrication using checks like DRC, LVS, and power analysis.
Indicative Content for Physical Design and Verification Program
| Foundation | Advanced Microelectronics | Synthesis & DFT | Physical Design & Verification | Career Guidance |
Linux Essentials Python Scripting TCL Scripting Digital Electronics High Speed Digital Design Logic Design Circuit Theory Network Theory Verilog for Synthesis
| Introduction to Microelectronics MOSFET MOSFET as switch, Cap, Amplifier Long Channel & Short Channel effects Small signal analysis Emerging MOS devices – CFET, GAA, FINFET SOI (Silicon-on-Insulator) Technology FD-SOI vs Bulk CMOS Advanced CMOS Nodes (5nm, 3nm, 2nm) Process Variations & Reliability Analysis Layout dependent effects -WPE, PPE, LOD Noise mitigation techniques 3D IC, Chiplet & Heterogeneous Integration | Introduction to Synthesis flow Introduction to EDA tools Timing Libraries Constraint setup & Optimization techniques Lint & Clock Domian Crossing Generating netlist & reports Static Timing Analysis Low power Analysis UPF Introduction to DFT Scan Chain Insertion, Scan Compression, Fault Models, ATPG BIST Architecture | Physical design Process Initial Design Floorplan Powerplan Placement Routing Clock Tree Synthesis Engineering Change Order(ECO) Physical Verification –DRC, LVS, Antenna Check, ERC, LEC Parasitic Extraction Back Annotation Power, Timing, Signal Integrity (SI), EM/IR analysis Signoff Project | Soft Skills Building Resume Mock Interviews Personality Development Report Writing |
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