Maven Silicon

Executive Certification in VLSI Design for Testing

Certification (IT & Software)

Shortlisted by 0+ Students

Location: Bengaluru/Bangalore

Duration: 9 MONTH

Online / Virtual

Average Fees: ₹ 2 Lakhs

Highlights With the advent of AI technology, chip designers are equipped with an arsenal of AI-based EDA tools, already verified IP libraries, and approachable hardware like RISC-V which will allow the design of efficient and powerful SoCs suitable for the next generation of products. Yet, testability and fault coverage are the two major areas of concern that have to be addressed if one wants to achieve success with the first pass of silicon. Now is the best period for the chip designers and VLSI aficionados to get acquainted with DFT (Design for Testing) techniques that include scanning, ATPG, fault modeling, BIST, boundary scanning, JTAG and the newest methods for low-power and high-performance designs. A solid grip on DFT translates to high-quality and reliable SoCs that are ready for large-scale manufacturing.

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