Maven Silicon
Executive Certification in VLSI Design for Testing
Certification (IT & Software)
Shortlisted by 0+ Students
Location: Bengaluru/Bangalore
Duration: 9 MONTH
Online / Virtual
Average Fees: ₹ 2 Lakhs
Highlights With the advent of AI technology, chip designers are equipped with an arsenal of AI-based EDA tools, already verified IP libraries, and approachable hardware like RISC-V which will allow the design of efficient and powerful SoCs suitable for the next generation of products. Yet, testability and fault coverage are the two major areas of concern that have to be addressed if one wants to achieve success with the first pass of silicon. Now is the best period for the chip designers and VLSI aficionados to get acquainted with DFT (Design for Testing) techniques that include scanning, ATPG, fault modeling, BIST, boundary scanning, JTAG and the newest methods for low-power and high-performance designs. A solid grip on DFT translates to high-quality and reliable SoCs that are ready for large-scale manufacturing.
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Executive Certification in VLSI Design for Testing - iHUB, IIT Roorkee
The course is structured meticulously, covering all the necessary topics in the field of Design For Testing. Initially, the participants get to see an outline of VLSI, Moore’s Law, SoC architecture, and design flows, which is then followed by the necessary digital logic fundamentals like number systems, combinational and sequential circuits, FSMs, and memory design. Progressive steps lead to practical hardware design and verification with the help of Verilog HDL programming - coding styles, FSM design, and lab exercises. After that, you will be introduced to the Chip Manufacturing Process where Digital Logic Design, Synthesis, Clock Domain Crossing, STA, Equivalence Checking, and Physical Design Flow - floor planning, placement, CTS, routing, layout compaction, and physical verification (DRC, LVS, IR drop, EM), labs, and case studies - will all be included. The module of Design For Testing that is specifically aimed at doing the verification of the circuits instead of just testing them also includes, among others, the scan insertion, ATPG, fault modeling, BIST, and boundary scan, DRC & test coverage, JTAG, DFT for analog macros, while the automation skills at the same time are being developed with Tcl and Python scripting. Guiding through the use of Git for version control embodies one of the steps which eventually lead to the understanding of advanced DFT concepts and participation in an industrial standard project – DFT implementation on an SoC.
Program Highlights
Executive Certification in VLSI Design for Testing with Placements Fees Details:
Total Fees for 9 Months Programme: INR 2,00,000 + GSP
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